(1) Field of the Invention
The invention generally relates to a method used in semiconductor memory manufacturing and, more particularly, to a method of erasing memory cells during testing in a flash electrically erasable programmable read only memory (EEPROM) in the fabrication of integrated circuits (ICs).
(2) Description of Prior Art
Electrically erasable EEPROMs, often referred to as “Flash” EPROM, have emerged as an important non-volatile memory. Having the same cell density as standard EPROMs, they have the advantage over EPROMs that they need not be exposed to ultraviolet (UV) light to be erased. This is also an advantage in that standard IC packages can be used for these devices whereas standard EPROMs require a special package allowing the IC die to be exposed to UV light.
In a standard Flash EPROM, a plurality of flash memory cells are arranged in an array of rows and columns. Refer now to FIG. 1 showing a typical flash memory cell device. Each cell 10 is composed of a p-type substrate 12 and separate n-type source 14 and drain 16 regions formed on the substrate 12. A p-type channel region 18 in the substrate 12 separates the source 14 and drain 16. A floating gate 20, electrically isolated from and positioned over the channel region 18, is separated from the substrate 12 by a thin dielectric layer 22. A control gate 24 is separated from the floating gate 20 by a second dielectric layer 26.
To program the flash EPROM cell, the drain and control gate are raised to voltages above the voltage applied to the source region. For example, the drain voltage (VD) and control gate voltage (VCG) are set to 5.5V and 9V above the source voltage, respectively. This produces hot electrons, which are transferred across the thin dielectric layer, trapping them on the floating gate. The control gate voltage threshold is the minimum voltage that must be applied to the control gate in order to affect conduction between the source and drain. This injection of hot electrons has the effect of raising the control gate threshold by about two to four volts.
To erase a flash EPROM cell, the source voltage (VS) is set to a positive voltage and the control gate voltage (VCG) is set to a negative voltage while the drain floats. Typically, the minimum normal source to control gate erase voltage (VNE) is 11 volts. An electric field forms between the source and floating gate thereby removing the negative charge on the floating gate by Fowler-Nordheim tunneling. The minimum erase voltage increases with the number of program and erasure cycles performed. This is depicted in FIG. 2 where the minimum erase voltage is approximately 11.2V at the time of manufacturing and increases to just under 13V after 90,000 erasures, In order to predict the proper operation of the device over the device lifetime, a lower voltage such as 12V is typically used during chip probe testing. This lower voltage test is referred to as marginal erase. If the memory will erase at this lower voltage at wafer probe, then it is statistically predicted that it will continue to erase at VNE for many thousands of erasures.
FIG. 3 schematically shows how the normal and margin erase voltages are typically generated. During normal operation, an erase voltage VE is generated from a charge pump circuitry and regulated by a regulator in the flash macro 42. For marginal erase testing, a fixed external voltage (VME) is applied to a test pad (30) to perform the marginal erase. VME is applied through resistor 32 by closing a switch 44 within the flash macro 42. Unfortunately, this requires placement of the additional test pad 30 to apply the marginal erase voltage (VME) during chip probe. In addition, since VME is fixed, it cannot compensate for changes observed in the normal erase voltage (VNE) due to process variations.
FIG. 4 illustrates the process variation in VNE and further demonstrates that using a fixed VME will result in a variation in the differences between VNE and VME. This reduces the effectiveness of the margin erase test in guaranteeing the endurance specification.
Other approaches related to improving memory device circuits exist. U.S. Pat. Nos. 4,809,231 and 4,903,265 to Shannon et al. describe methods for post-package testing of one-time-programmable (OTP) EPROM memories where cells are marginally programmed to demonstrate that they are addressable. This is accomplished by applying special programming voltages such that the cell threshold changes slightly, but not enough to exceed the maximum erased specification. U.S. Pat. No. 5,142,495 to Canepa teaches a margining circuit in an EPROM where a plurality of parallel transistors form a variable load. This effectively adjusts the current applied to the memory cell. U.S. Pat. No. 5,369,616 to Wells et al. teaches a method where non-volatile memory is used to set memory system parameters such as threshold, word length, and addressing scheme. U.S. Pat. No. 5,544,116 to Chao et al. teaches a method of verifying program states of Flash EPROM cells where different voltages are applied to the reference and memory cells. This controls the ratio of the currents in those cells making cell verification more accurate. U.S. Pat. No. 5,675,537 to Bill et al. teaches a method where overerasure of memory cells in a Flash EPROM is prevented by halting erasure once a prescribed cell threshold is reached. U.S. Pat. No. 5,870,407 to Hsia et al. teaches a method of predicting high temperature failures of Flash EPROM memory devices that reduces testing time and packaging cost. U.S. Pat. No. 6,122,198 to Haddad et al. teaches a method for guaranteeing that an erased cell threshold voltage in a two bit per cell Flash EPROM falls within prescribed limits. This is accomplished by testing for both over and under erase conditions until all cells pass satisfactorily.